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74LCX126 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
September 2000 Revised May 2005
74LCX126 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
General Description
The LCX126 contains four independent non-inverting buffers with 3-STATE outputs. Each output is disabled when the associated output-enable (OE) input is LOW. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX126 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V-3.6V VCC specifications provided s 5.5 ns tPD max (VCC
3.3V), 10 PA ICC max
s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r24 mA output drive (VCC
3.0V)
s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds JEDEC 78 conditions s ESD performance:
Human body model ! 2000V Machine model ! 100V
s Leadless Pb-Free DQFN package
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to GND through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX126M 74LCX126SJ 74LCX126BQX (Note 2) 74LCX126MTC 74LCX126MTCX_NL (Note 3) Package Number M14A M14D MLP014A MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 2: DQFN package available in Tape and Reel only. Note 3: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.
(c) 2005 Fairchild Semiconductor Corporation
DS500386
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74LCX126
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Logic Symbol
IEEE/IEC
Pin Descriptions
(Top View) Pad Assignments for DQFN Pin Names An OEn On Description Inputs Output Enable Inputs Outputs
Truth Table
Inputs OEn H H L
H HIGH Voltage Level L LOW Voltage Level Z X
Output An L H X
High Impedance Immaterial
On L H Z
(Top Through View)
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74LCX126
Absolute Maximum Ratings(Note 4)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI GND VO GND VO ! VCC V V mA mA mA mA mA
0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 6)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V
r24 r12 r8 40
0 85 10
mA
qC
ns/V
't/'V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Conditions VCC (V) 2.3 2.7 2.7 3.6 2.3 2.7 2.7 3.6 TA
40qC to 85qC
Max
Min 1.7 2.0
Units V
0.7 0.8 VCC 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55
V
100 PA 12 mA 18 mA 24 mA
100 PA 12 mA 16 mA 24 mA
2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 3.6 0
IOH = -8 mA
V
IOL = 8mA
V
0 d VI d 5.5V 0 d VO d 5.5V VI V IH or VIL 5.5V VI or VO
r5.0 r5.0
10
PA PA PA
3
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74LCX126
DC Electrical Characteristics
Symbol ICC Parameter Quiescent Supply Current Increase in ICC per Input VI VIH
(Continued)
VCC (V) VCC or GND VCC 0.6V 2.3 3.6 2.3 3.6 2.3 3.6 TA
Conditions
40qC to 85qC
Max 10
Units
Min
3.6V d VI, VO d 5.5V (Note 7)
r10
500
PA PA
'ICC
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA Symbol Parameter VCC CL Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 8) Output Disable Time Output Enable Time Propagation Delay 1.5 1.5 1.5 1.5 1.5 1.5 3.3V r 0.3V 50 pF Max 5.5 5.5 6.0 6.0 5.5 5.5 1.0 1.0
40qC to 85qC, RL
VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.7V 50 pF Max 6.0 6.0 7.0 7.0 6.5 6.5
500: VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.5V r 0.2V 30 pF Max 6.6 6.6 7.8 7.8 6.6 6.6 ns ns ns ns Units
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30 pF, VIH 50 pF, VIH 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC Typical 0.8 0.6 Units V V
0.8 0.6
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 25 Units pF pF pF
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74LCX126
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms (Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
5
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74LCX126
Schematic Diagram Generic for LCX Family
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74LCX126
Tape and Reel Specification
Tape Format for DQFN Package Designator BQX Tape Section Leader (Start End) Carrier Trailer (Hub End) TAPE DIMENSIONS inches (millimeters) Number Cavities 125 (typ) 2500/3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed
REEL DEMENSIONS Inches (millimeters)
Tape Size 12mm
A 13.0 (330)
B 0.059 (1.50)
C 0.512 (13.00)
D 0.795 (20.20)
N 7.008 (178)
W1 0.488 (12.4)
W2 0.724 (18.4)
7
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74LCX126
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74LCX126
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
9
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74LCX126
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package Number MLP014A
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74LCX126 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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